US 11,868,253 B2
Memory device interface and method
Brent Keeth, Boise, ID (US); Owen Fay, Meridian, ID (US); Chan H. Yoo, Boise, ID (US); Roy E. Greeff, Boise, ID (US); and Matthew B. Leslie, Boise, ID (US)
Filed by Lodestar Licensing Group, LLC, Evanston, IL (US)
Filed on Jul. 11, 2022, as Appl. No. 17/861,627.
Application 17/861,627 is a continuation of application No. 16/797,618, filed on Feb. 21, 2020, granted, now 11,386,004.
Claims priority of provisional application 62/826,422, filed on Mar. 29, 2019.
Claims priority of provisional application 62/816,731, filed on Mar. 11, 2019.
Claims priority of provisional application 62/809,281, filed on Feb. 22, 2019.
Prior Publication US 2022/0342814 A1, Oct. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G06F 12/06 (2006.01); G11C 29/12 (2006.01); G11C 11/4093 (2006.01); H01L 25/18 (2023.01); H01L 25/065 (2023.01); G06F 12/02 (2006.01)
CPC G06F 12/0653 (2013.01) [G06F 12/0215 (2013.01); G11C 11/4093 (2013.01); G11C 29/12 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); G06F 2212/1016 (2013.01); G11C 2211/4062 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a processor coupled to a first substrate;
a memory device coupled to the first substrate adjacent to the processor, the memory device including:
a buffer device coupled to a second substrate, the buffer device including a host interface, and a DRAM interface wherein the host interface includes at least one memory channel, and wherein the DRAM interface includes at least two sub-channels;
a stack of multiple DRAM dies coupled to the second substrate; and
circuitry in the buffer device, configured to operate the host interface at a first data speed, and to operate the DRAM interface at a second data speed, slower than the first data speed, the circuitry configured to map the at least one memory channel to the at least two sub-channels.