US 11,868,252 B2
Memory with post-packaging master die selection
Evan C. Pearson, Boise, ID (US); John H. Gentry, Boise, ID (US); Michael J. Scott, Boise, ID (US); Greg S. Gatlin, Mountain Home, ID (US); Lael H. Matthews, Meridian, ID (US); Anthony M. Geidl, Boise, ID (US); Michael Roth, Boise, ID (US); Markus H. Geiger, Boise, ID (US); and Dale H. Hiscock, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 6, 2019, as Appl. No. 16/706,635.
Prior Publication US 2021/0173773 A1, Jun. 10, 2021
Int. Cl. G06F 11/07 (2006.01); G06F 12/06 (2006.01); H01L 25/065 (2023.01); G11C 11/407 (2006.01); G11C 29/04 (2006.01)
CPC G06F 12/0646 (2013.01) [G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G06F 11/0793 (2013.01); G11C 11/407 (2013.01); G11C 29/04 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06541 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of memory dies, each memory die of the plurality of memory dies including:
command/address decoders coupled to external contacts of the memory device and configured to (a) receive command and address signals from the external contacts and (b) when enabled, to decode the command and address signals and to transmit the decoded command and address signals to other memory dies of the plurality of memory dies; and
master selection circuitry configured to enable, or disable, or both corresponding command/address decoders of a respective memory die,
wherein the command/address decoders of the plurality of memory dies are each enabled or disabled via the corresponding master selection circuitry based at least in part on differences between one or more process corners of memory dies of the plurality of memory dies.