US 11,868,245 B2
Pre-load techniques for improved sequential memory access in a memory device
Xinghui Duan, Shanghai (CN); Bin Zhao, Shanghai (CN); and Jianxiong Huang, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/272,113
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Sep. 21, 2020, PCT No. PCT/CN2020/116462
§ 371(c)(1), (2) Date Feb. 26, 2021,
PCT Pub. No. WO2021/184714, PCT Pub. Date Sep. 23, 2021.
Application 17/272,113 is a continuation in part of application No. PCT/CN2020/079414, filed on Mar. 15, 2020.
Claims priority of application No. PCT/CN2020/079414 (WO), filed on Mar. 15, 2020.
Prior Publication US 2022/0300409 A1, Sep. 22, 2022
Int. Cl. G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 13/16 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 12/0623 (2013.01); G06F 13/1668 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7203 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method performed by a memory device, the method comprising:
receiving a first memory access command from a host, the first memory access command to access a memory array of the memory device;
determining that the first memory access command is a sequential read command;
determining whether an LBA-to-physical address (L2P) region of an L2P cache includes a first LBA received with the first memory access command;
in response to determining the first LBA of the first memory access command is not within the L2P cache and that the first memory access command is a sequential read command, performing one load of multiple L2P regions of an L2P table from the memory array to the L2P cache;
determining a first physical address of the memory array based on the first LBA and at least a first L2P region of the multiple L2P regions within the L2P cache; and
executing the first memory access command based on the first physical address.