US 11,868,211 B2
Error detection and correction in memory
Joseph M. McCrate, Boise, ID (US); and Robert J. Gleixner, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 26, 2022, as Appl. No. 17/953,247.
Application 17/953,247 is a continuation of application No. 17/239,864, filed on Apr. 26, 2021, granted, now 11,455,210.
Prior Publication US 2023/0014459 A1, Jan. 19, 2023
Int. Cl. G06F 11/10 (2006.01); G11C 13/00 (2006.01); H03M 13/15 (2006.01)
CPC G06F 11/1076 (2013.01) [G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); H03M 13/152 (2013.01); G11C 2213/15 (2013.01)] 20 Claims
OG exemplary drawing
 
7. A method of operating memory, comprising:
performing a first sense operation using a first voltage on a group of self-selecting memory cells comprising a word to sense data from the group of self-selecting memory cells; and
performing a second sense operation using a second voltage having an opposite polarity from the first voltage on the group of self-selecting memory cells after the first sense operation to identify memory cells of the group that cannot store data;
marking bits in the word corresponding to the identified memory cells of the group as erasures.