| CPC G06F 1/324 (2013.01) [G06F 1/08 (2013.01); H03K 5/135 (2013.01); G06F 1/3203 (2013.01)] | 18 Claims |
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1. Adaptive frequency scaling circuitry configured to generate a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency, the adaptive frequency scaling circuitry comprising:
scaling control circuitry comprising hardware configured to:
identify a hardware operating parameter of the data processing system;
adjust the dynamic clock signal frequency of the dynamic clock signal in view of the hardware operating parameter of the data processing system; and
select a dynamic clock gating control value indicative of an integer N; and
clock gating circuitry comprising:
accumulator circuitry having M+1 bits, wherein the accumulator is configured to combine a first input value and a second input value and output M+1 bits corresponding to a sum of the first value and the second value, further wherein the first input value is N;
register circuitry configured to store bits M−1 to 0 of the output M+1 bits from the accumulator and provide the stored bits to the accumulator as the second value; and
gate circuitry configured to output the dynamic clock signal by passing an input clock signal pulse in response to bit M in the output M+1 bits from the accumulator being 1, wherein the scaling control circuitry is configured to determine N based at least on a desired frequency and M.
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