CPC G06F 1/10 (2013.01) [H01L 24/02 (2013.01); H01L 2224/08145 (2013.01)] | 20 Claims |
1. A multi-chip device comprising:
a chip stack comprising chips, the chip stack comprising a clock tree, in-chip routing of the clock tree being contained within one logical chip of the chip stack, the chip stack comprising leaf nodes disposed in respective chips, each leaf node of the leaf nodes being electrically connected to the clock tree through a respective leaf-level connection bridge, each leaf-level connection bridge configured to couple and decouple in-chip routing of a respective leaf node to and from a metal stack of the clock tree, the respective leaf-level connection bridge extending in an out-of-chip direction through a plurality of the chips.
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