US 11,867,758 B2
Test method for control chip and related device
Chuanqi Shi, Hefei (CN); Heng-Chia Chang, Hefei (CN); Li Ding, Hefei (CN); Jie Liu, Hefei (CN); Jun He, Hefei (CN); and Zhan Ying, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/595,452
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Oct. 15, 2020, PCT No. PCT/CN2020/121294
§ 371(c)(1), (2) Date Nov. 17, 2021,
PCT Pub. No. WO2021/179601, PCT Pub. Date Sep. 16, 2021.
Claims priority of application No. 202010166586.4 (CN), filed on Mar. 11, 2020.
Prior Publication US 2022/0214397 A1, Jul. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G01R 31/3193 (2006.01); G01R 31/319 (2006.01); G11C 29/56 (2006.01); G01R 31/28 (2006.01); G01R 31/3187 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/2834 (2013.01); G01R 31/2856 (2013.01); G01R 31/3187 (2013.01); G01R 31/3193 (2013.01); G01R 31/31713 (2013.01); G01R 31/31724 (2013.01); G01R 31/31917 (2013.01); G01R 31/31932 (2013.01); G01R 31/318566 (2013.01); G11C 29/56 (2013.01); G11C 2029/5602 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A test method for a control chip, the control chip comprising a built-in self-test (BIST) circuit, and the test method being performed by the BIST circuit, wherein the test method comprises:
acquiring a current status of a memory chip in a storage device;
using the memory chip in an idle state as a first target memory chip when the current status of the memory chip is the idle state, to store at least some of test vectors used for testing the control chip as first test vectors in the first target memory chip, wherein the idle state is a status of the memory chip when the memory chip currently has not stored any data;
reading the first test vectors stored in the first target memory chip;
sending the first test vectors to the control chip;
receiving first output information returned by the control chip in response to the first test vectors; and
acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information.