US 11,867,746 B2
Failure detection system for integrated circuit components
Thomas P. Joyce, Rockford, IL (US); and Ashutosh Joshi, Roscoe, IL (US)
Assigned to Hamilton Sundstrand Corporation, Charlotte, NC (US)
Filed by Hamilton Sundstrand Corporation, Charlotte, NC (US)
Filed on Sep. 14, 2021, as Appl. No. 17/475,299.
Prior Publication US 2023/0090583 A1, Mar. 23, 2023
Int. Cl. G01R 31/28 (2006.01); G01R 19/00 (2006.01)
CPC G01R 31/2803 (2013.01) [G01R 19/0092 (2013.01); G01R 31/2856 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A method for detecting component failure in an integrated circuit, comprising:
determining an actual current output of an integrated circuit component in a first state;
determining an actual condition of the integrated circuit component in the first state;
comparing the actual current output to a fixed reference representing a minimum acceptable current of the component in the first state to generate a first compared result;
comparing the actual condition of the integrated circuit component to a fixed reference representing a maximum acceptable value of the condition at which the component can enter a second state to generate a second compared result;
comparing the actual condition of the integrated circuit component to a fixed reference representing a minimum acceptable value of the condition at which the component can enter the second state to generate a third compared result; and
outputting a component failed state signal based at least in part on the first, second, and third compared results, wherein outputting the component failed state signal includes:
outputting a first component failed state signal if:
the actual current output of the component is above the fixed reference representing the minimum acceptable current of the component in the first state; and
the actual condition of the component is less than the fixed reference representing the minimum acceptable value of the condition at which the component can enter the second state; and
outputting a second component failed state signal if:
the actual current of the component is above the fixed reference representing the minimum acceptable current of the component in the first state; and
the actual condition of the component is greater than the fixed reference representing the maximum acceptable value of the condition at which the component can enter the second state,
wherein the first component failed state signal is different than the second component failed state signal.