US 11,867,745 B2
Parasitic capacitance detection method, memory and readable storage medium
Shibing Qian, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Nov. 22, 2021, as Appl. No. 17/455,969.
Application 17/455,969 is a continuation of application No. PCT/CN2021/106511, filed on Jul. 15, 2021.
Claims priority of application No. 202011108280.X (CN), filed on Oct. 16, 2020.
Prior Publication US 2022/0120806 A1, Apr. 21, 2022
Int. Cl. G01R 31/26 (2020.01); G01R 27/26 (2006.01); H10B 12/00 (2023.01)
CPC G01R 31/2601 (2013.01) [G01R 27/2605 (2013.01); H10B 12/00 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A method for detecting a parasitic capacitance in a semiconductor device, the semiconductor device being provided with sources, drains, active layers, gates located on the active layers, and wires connected to the sources and the drains, the method for detecting the parasitic capacitance in the semiconductor device comprising:
providing a plurality of semiconductor devices for testing, all the semiconductor devices being the same in a number of sources, a number of drains, a number of active layers, a number of gates, a number of wires and a cross-sectional area of the wire, all the semiconductor devices being different in a length of the wire therein;
obtaining a total capacitance value of each of the plurality of semiconductor devices and the length of the wire in the each semiconductor device;
determining a capacitance between the wire per unit length and the gate in the semiconductor device according to the plurality of total capacitance values and the lengths of the plurality of the wire of the plurality of semiconductor devices, the capacitance between the wire per unit length and the gate being considered as a parasitic capacitance per unit length;
determining a corresponding wire length of a to-be-detected semiconductor device; and
determining a parasitic capacitance of the to-be-detected semiconductor device according to the parasitic capacitance per unit length and the corresponding wire length of the to-be-detected semiconductor device.