US 11,867,744 B2
Techniques for isolating interfaces while testing semiconductor devices
Animesh Khare, Bangladore (IN); Ashish Kumar, Patna (IN); Shantanu Sarangi, Saratoga, CA (US); Rahul Garg, Jind (IN); and Sailendra Chadalavada, Saratoga, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on Oct. 20, 2020, as Appl. No. 17/075,629.
Prior Publication US 2022/0120804 A1, Apr. 21, 2022
Int. Cl. G01R 31/26 (2020.01); G01R 31/317 (2006.01); G01R 31/3183 (2006.01); G01R 31/3185 (2006.01); G06F 13/42 (2006.01)
CPC G01R 31/2601 (2013.01) [G01R 31/2639 (2013.01); G01R 31/31725 (2013.01); G01R 31/318328 (2013.01); G01R 31/318536 (2013.01); G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for testing a semiconductor device, comprising:
causing a clock control unit to stop transmitting clock signals to an interface circuit that resides within the semiconductor device and couples the semiconductor device to a high-speed data transfer connection;
after the clock control unit has stopped transmitting the clock signals, causing the interface circuit to be isolated from portions of the semiconductor device; and
after waiting for a first predetermined period of time to expire, causing the clock control unit to start transmitting clock signals again to the interface circuit.