CPC H10B 41/27 (2023.02) [G11C 5/025 (2013.01); G11C 16/0483 (2013.01); G11C 16/3436 (2013.01); H10B 43/27 (2023.02)] | 14 Claims |
1. A control method of a three-dimensional memory, the three-dimensional memory comprising a first deck and a second deck that are stacked in a vertical direction of a substrate, the first deck and the second deck each comprising a plurality of memory strings, each memory string comprising a plurality of memory cells, the plurality of memory cells comprising a first portion and a second portion, wherein a diameter of a channel structure corresponding to the first portion of memory cells is smaller than that of the channel structure corresponding to the second portion of memory cells, the method comprising:
performing a read operation for selected memory cells which are in at least one of the first deck or the second deck; and
applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck, the pass voltage comprising a first pass voltage and a second pass voltage, the first pass voltage being lower than the second pass voltage, wherein the first pass voltage is applied to first non-selected memory cells in the first portion, and the second pass voltage is applied to second non-selected memory cells in the second portion.
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