US 11,864,374 B2
Semiconductor memory device
Jin Sun Cho, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Oct. 1, 2021, as Appl. No. 17/491,971.
Claims priority of application No. 10-2021-0029443 (KR), filed on Mar. 5, 2021.
Prior Publication US 2022/0285353 A1, Sep. 8, 2022
Int. Cl. H10B 12/00 (2023.01); H01L 29/786 (2006.01)
CPC H10B 12/30 (2023.02) [H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10B 12/50 (2023.02); H01L 29/7869 (2013.01); H01L 29/78672 (2013.01); H01L 29/78684 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
an active layer spaced apart from a substrate wherein the active layer extends in a direction parallel to the substrate and includes a channel;
a bit line extending in a direction perpendicular to the substrate and coupled to a first end of the active layer;
a capacitor coupled to an end of a second end of the active layer;
a double word line including a pair of dual work function electrodes extending in a direction crossing the active layer with the active layer interposed therebetween; and
a gate dielectric layer formed between the active layer and the double word line,
wherein each of the dual work function electrodes includes:
a high work function electrode which is adjacent to the bit line; and
a low work function electrode which is adjacent to the capacitor and having a lower work function than the high work function electrode,
wherein the high work function electrode is in direct contact with the low work function electrode.