US 11,863,816 B2
Methods, articles of manufacture, and apparatus to edit tuning data collected via automated content recognition
Samantha M. Mowrer, La Grange, IL (US); Fatemehossadat Miri, Chicago, IL (US); Balachander Shankar, Tampa, FL (US); David J. Kurzynski, Elgin, IL (US); Hariprasath Balasubramani, Odessa, FL (US); Sharan Senthilvasan, Tampa, FL (US); Lisa G. Rossi, Lutz, FL (US); Mike Anderson, Chicago, IL (US); and Abhignya Goje, Chicago, IL (US)
Assigned to The Nielsen Company (US), LLC, New York, NY (US)
Filed by The Nielsen Company (US), LLC, New York, NY (US)
Filed on Jul. 29, 2022, as Appl. No. 17/877,589.
Claims priority of provisional application 63/300,629, filed on Jan. 18, 2022.
Prior Publication US 2023/0232067 A1, Jul. 20, 2023
Int. Cl. H04N 21/44 (2011.01); H04N 21/45 (2011.01); H04N 21/442 (2011.01); H04N 21/4425 (2011.01); H04N 21/258 (2011.01)
CPC H04N 21/44008 (2013.01) [H04N 21/25841 (2013.01); H04N 21/25866 (2013.01); H04N 21/442 (2013.01); H04N 21/4425 (2013.01); H04N 21/44204 (2013.01); H04N 21/44222 (2013.01); H04N 21/4524 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus to edit tuning data collected via automated content recognition, the apparatus comprising:
interface circuitry to obtain the tuning data to be edited from a presentation device; and
processor circuitry including one or more of:
at least one of a central processor unit, a graphics processor unit, or a digital signal processor, the at least one of the central processor unit, the graphics processor unit, or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus;
a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and the plurality of the configurable interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations; or
Application Specific Integrated Circuitry (ASIC) including logic gate circuitry to perform one or more third operations;
the processor circuitry to perform at least one of the first operations, the second operations, or the third operations to instantiate:
view conflict resolution circuitry to:
determine whether a time conflict exists between first tuning data corresponding to a first tuning event and second tuning data corresponding to a second tuning event, the first tuning data and the second tuning data collected by the presentation device via automated content recognition, the time conflict including a period of overlap associated with the first tuning event and the second tuning event;
in response to determining that the time conflict exists, create a third tuning event based on the first tuning data or the second tuning data, the third tuning event created based on one or more criteria; and
modify the first tuning event and the second tuning event based on the third tuning event; and
audience measurement circuitry to analyze edited tuning data to measure audience viewing behaviors, the edited tuning data including the first modified tuning event, the second modified tuning event, and the third tuning event.