| CPC H04N 19/176 (2014.11) [H04N 19/122 (2014.11); H04N 19/159 (2014.11); H04N 19/18 (2014.11); H04N 19/61 (2014.11)] | 3 Claims |
|
1. A video decoding device for decoding a video, the video decoding device comprising:
a memory; and
a processor configured or programmed to execute instructions stored in the memory to:
decode coded data and output quantization transform coefficients;
perform an inverse quantization on the quantization transform coefficients and output secondary two-dimensional transform coefficients;
arrange at least a portion of the secondary two-dimensional transform coefficients into secondary one-dimensional transform coefficients;
perform an inverse secondary transform on the secondary one-dimensional transform coefficients and output primary one-dimensional inverse transform coefficients;
arrange the primary one-dimensional inverse transform coefficients into primary two-dimensional inverse transform coefficients; and
perform an inverse primary transform on the primary two-dimensional inverse transform coefficients, wherein,
if a width of a secondary two-dimensional transform coefficients block is less than a predefined value or a height of the secondary two-dimensional transform coefficients block is less than the predefined value, the primary one-dimensional inverse transform coefficients are stored in a squared region,
otherwise the primary one-dimensional inverse transform coefficients are stored in a non-squared region.
|