US 11,863,569 B2
Bus-off attack prevention circuit
Marcio Rogerio Juliato, Portland, OR (US); Shabbir Ahmed, Beaverton, OR (US); Santosh Ghosh, Hillsboro, OR (US); Christopher Gutierrez, Hillsboro, OR (US); and Manoj R. Sastry, Portland, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 17, 2021, as Appl. No. 17/529,020.
Application 17/529,020 is a continuation of application No. 16/402,535, filed on May 3, 2019, granted, now 11,201,878.
Claims priority of provisional application 62/760,726, filed on Nov. 13, 2018.
Prior Publication US 2022/0078201 A1, Mar. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 29/06 (2006.01); H04L 12/40 (2006.01); H04L 9/40 (2022.01)
CPC H04L 63/1416 (2013.01) [H04L 12/40 (2013.01); H04L 12/40136 (2013.01); H04L 63/1466 (2013.01); H04L 2012/40215 (2013.01)] 42 Claims
OG exemplary drawing
 
1. An electronic device for bus-off attack detection and prevention, the electronic device comprising:
bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry disposed between the protected node and the bus, and to serve as a dedicated proxy for the protected node, the bus-off prevention circuitry to:
detect a transmitted message from the protected node to the bus;
detect a bit mismatch of the transmitted message on the bus;
suspend further transmissions from the protected node while the bus is analyzed by using a bypass channel to transmit the transmitted message back to the protected node;
determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and
signal the protected node indicating whether a fault has occurred, wherein the bus-off prevention circuitry uses the bypass channel to transmit an altered message back to the protected node, the altered message including a bit flipped from the transmitted message such that further transmission from the protected node is suspended.