US 11,863,346 B2
Signaling of time for communication between integrated circuits using multi-drop bus
Helena Deirdre O'Shea, San Jose, CA (US); Matthias Sauer, San Jose, CA (US); and Jorge L. Rivera Espinoza, San Jose, CA (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jan. 30, 2023, as Appl. No. 18/103,137.
Application 18/103,137 is a continuation of application No. 17/854,979, filed on Jun. 30, 2022, granted, now 11,595,230.
Application 17/854,979 is a continuation of application No. 16/885,966, filed on May 28, 2020, granted, now 11,398,926, issued on Jul. 26, 2022.
Claims priority of provisional application 62/972,566, filed on Feb. 10, 2020.
Prior Publication US 2023/0171126 A1, Jun. 1, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 12/40 (2006.01); H04L 12/413 (2006.01)
CPC H04L 12/4135 (2013.01) [H04L 12/40071 (2013.01); H04L 12/40084 (2013.01); H04L 2012/40215 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A first integrated circuit, comprising:
an interface circuit configured to:
receive timing packets from a second integrated circuit over a multi-drop bus, the timing packets indicating times at which periodic events occur at the second integrated circuit, and
determine delays in receiving the timing packets due to unsuccessful arbitration for transmitting the timing packets over the multi-drop bus; and
a synchronization generator circuit configured to generate one or more timing signals indicating when one or more periodic events are expected to occur at the second integrated circuit according to the received timing packets and the determined delays.