CPC H04L 12/4135 (2013.01) [H04L 12/40071 (2013.01); H04L 12/40084 (2013.01); H04L 2012/40215 (2013.01)] | 20 Claims |
1. A first integrated circuit, comprising:
an interface circuit configured to:
receive timing packets from a second integrated circuit over a multi-drop bus, the timing packets indicating times at which periodic events occur at the second integrated circuit, and
determine delays in receiving the timing packets due to unsuccessful arbitration for transmitting the timing packets over the multi-drop bus; and
a synchronization generator circuit configured to generate one or more timing signals indicating when one or more periodic events are expected to occur at the second integrated circuit according to the received timing packets and the determined delays.
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