US 11,863,284 B2
Systems and methods for post-detect combining of a plurality of downlink signals representative of a communication signal
Jeffrey David Jarriel, San Diego, CA (US); Daniel Joseph Sutton, San Diego, CA (US); Matthew James Stoltenberg, San Diego, CA (US); and Brandon Gregory King, San Diego, CA (US)
Assigned to KRATOS INTEGRAL HOLDINGS, LLC, San Diego, CA (US)
Filed by KRATOS INTEGRAL HOLDINGS, LLC, San Diego, CA (US)
Filed on May 27, 2021, as Appl. No. 17/332,349.
Application 17/332,349 is a continuation of application No. PCT/US2021/033867, filed on May 24, 2021.
Prior Publication US 2022/0385353 A1, Dec. 1, 2022
Int. Cl. H04B 7/08 (2006.01); G06F 11/14 (2006.01)
CPC H04B 7/0885 (2013.01) [G06F 11/1415 (2013.01); G06F 2201/86 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for combining a plurality of downlink signals representative of a communication signal, the method comprising:
receiving samples of the plurality of downlink signals from a plurality of antenna feeds;
generating first symbols for a first signal of the plurality of downlink signals based on performing a first timing recovery operation on first samples of the first signal;
generating second symbols for a second signal of the plurality of downlink signals based on performing a second timing recovery operation on second samples of the second signal;
generating time and phase offset information based on performing a correlator operation on the first and second symbols; and
combining the first signal and the second signal based on (i) the first and second symbols, (ii) aligning timing and phase of the first symbols with the second symbols based on the time and phase offset information, and (iii) performing a weighted combiner operation that applies scaling to each of the first and second signals based on corresponding signal quality,
wherein at least one of the first timing recovery operation, the second timing recovery operation, the correlator operation, and the combing are performed in a plurality of processing blocks in one or more processors, wherein the first and second processing block operate in parallel.