US 11,863,198 B2
Successive approximation register analog to digital converter with reduced data path latency
Ullas Singh, Irvine, CA (US); Namik Kocaman, Irvine, CA (US); Mohammadamin Torabi, Mission Viejo, CA (US); Meisam Honarvar Nazari, Irvine, CA (US); Mehmet Batuhan Dayanik, Irvine, CA (US); Delong Cui, Irvine, CA (US); and Jun Cao, Irvine, CA (US)
Assigned to Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed by Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed on Mar. 21, 2022, as Appl. No. 17/699,678.
Prior Publication US 2023/0299781 A1, Sep. 21, 2023
Int. Cl. H03M 1/06 (2006.01)
CPC H03M 1/0697 (2013.01) [H03M 1/0678 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a digital to analog conversion (DAC) circuit;
a comparator circuit coupled to the DAC circuit having an output;
a first set of storage circuits coupled to the comparator circuit and the DAC circuit, the first set of storage circuits is configured to store a plurality of first bits corresponding to an input voltage; and
a comparator driver between the output and the first set of storage circuits, wherein the comparator driver comprises a first driver and second driver, the first driver being coupled to an input of a first storage circuit of the first set of storage circuits, and the second driver being coupled to inputs of a second set of storage circuits within the first set of storage circuits.