CPC H03L 7/0995 (2013.01) [G04F 10/005 (2013.01); H03K 3/037 (2013.01); H03K 19/017509 (2013.01); H03M 7/16 (2013.01); H03L 2207/50 (2013.01)] | 20 Claims |
1. A system, comprising:
a phase locked loop comprising:
a set of inverters; and
a set of flops, wherein each flop of the set of flops is coupled to an output of a different inverter of the set of inverters; and
a decoder configured to:
receive a code from the set of flops, wherein the code represents a phase of the phase locked loop;
responsive to the code being invalid, decode the invalid code to a valid code; and
provide the valid code to a phase frequency detector.
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