US 11,863,192 B2
Radio-frequency (RF) apparatus for digital frequency synthesizer including sigma-delta modulator and associated methods
John M. Khoury, Austin, TX (US)
Assigned to Silicon Laboratories Inc., Austin, TX (US)
Filed by Silicon Laboratories Inc., Austin, TX (US)
Filed on Jun. 30, 2022, as Appl. No. 17/855,537.
Application 17/855,537 is a continuation of application No. 16/221,436, filed on Dec. 14, 2018.
Prior Publication US 2022/0337255 A1, Oct. 20, 2022
Int. Cl. H03L 7/099 (2006.01); H03L 7/085 (2006.01); G06F 1/02 (2006.01); H03B 5/12 (2006.01); H03L 7/14 (2006.01); H03L 7/189 (2006.01); H03L 7/197 (2006.01)
CPC H03L 7/0991 (2013.01) [G06F 1/022 (2013.01); H03B 5/1206 (2013.01); H03B 5/1212 (2013.01); H03B 5/1218 (2013.01); H03B 5/1228 (2013.01); H03B 5/1243 (2013.01); H03B 5/1265 (2013.01); H03L 7/085 (2013.01); H03L 7/099 (2013.01); H03L 7/0992 (2013.01); H03L 7/148 (2013.01); H03L 7/189 (2013.01); H03L 7/1974 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising: a radio frequency (RF) receiver, the RF receiver comprising: an analog to digital converter (ADC); a digital frequency synthesizer (DFS) comprising a sigma-delta modulator (SDM) having three modes of operation; wherein a fractional divide parameter (n) is provided as an input to the SDM; wherein the SDM operates in a first mode, a second mode, or a third mode of the three modes of operation according to a value of the fractional divide parameter (n); and wherein the DFS provides a clock signal to the ADC.