CPC H03L 7/0991 (2013.01) [G06F 1/022 (2013.01); H03B 5/1206 (2013.01); H03B 5/1212 (2013.01); H03B 5/1218 (2013.01); H03B 5/1228 (2013.01); H03B 5/1243 (2013.01); H03B 5/1265 (2013.01); H03L 7/085 (2013.01); H03L 7/099 (2013.01); H03L 7/0992 (2013.01); H03L 7/148 (2013.01); H03L 7/189 (2013.01); H03L 7/1974 (2013.01)] | 20 Claims |
1. An apparatus comprising: a radio frequency (RF) receiver, the RF receiver comprising: an analog to digital converter (ADC); a digital frequency synthesizer (DFS) comprising a sigma-delta modulator (SDM) having three modes of operation; wherein a fractional divide parameter (n) is provided as an input to the SDM; wherein the SDM operates in a first mode, a second mode, or a third mode of the three modes of operation according to a value of the fractional divide parameter (n); and wherein the DFS provides a clock signal to the ADC.
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