US 11,863,191 B2
Combining voltage ramps to create linear voltage ramp
Joseph H. Colles, Bonsall, CA (US); and Steven E. Rosenbaum, San Diego, CA (US)
Assigned to Silanna Asia Pte Ltd, Singapore (SG)
Filed by Silanna Asia Pte Ltd, Singapore (SG)
Filed on Oct. 7, 2022, as Appl. No. 17/938,745.
Application 17/938,745 is a continuation of application No. 17/248,873, filed on Feb. 11, 2021, granted, now 11,496,121.
Application 17/248,873 is a continuation of application No. 16/384,632, filed on Apr. 15, 2019, granted, now 10,924,092, issued on Feb. 16, 2021.
Prior Publication US 2023/0034405 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 4/50 (2006.01); H03K 7/08 (2006.01)
CPC H03K 4/50 (2013.01) [H03K 7/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A ramp generator comprising:
a plurality of capacitors and a plurality of current sources that generate a plurality of voltage ramp signals in a plurality of sequential time periods, each voltage ramp signal being generated in a corresponding one of the sequential time periods; and
a set of switches that produce an output voltage ramp signal by repeatedly enabling generation of the plurality of voltage ramp signals in the corresponding sequential time periods and electrically connecting each one of the plurality of capacitors in a repeated sequence to an output node at which the output voltage ramp signal is produced.