US 11,863,187 B2
D-type wholly dissimilar high-speed static set-reset flip flop
Pradip Jadhav, Karnataka (IN); and Michael McManus, Hamilton, OH (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jun. 3, 2022, as Appl. No. 17/832,090.
Claims priority of provisional application 63/196,522, filed on Jun. 3, 2021.
Prior Publication US 2022/0399881 A1, Dec. 15, 2022
Int. Cl. H03K 3/037 (2006.01)
CPC H03K 3/0372 (2013.01) 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first master stage comprising a data input line;
a second master stage comprising an inverse data input line;
a first slave stage coupled to an output of the first master stage; and
a second slave stage coupled to an output of the second master stage, wherein the first slave stage is configured to generate an output signal during a rising edge of a clock cycle of a clock signal and the second slave stage is configured to generate an inverted output signal during the rising edge of the clock cycle and wherein the output signal and the inverted output signal are available concurrently; and
a cross-coupled circuit, wherein the cross-coupled circuit is coupled between an output of the first master stage and the output of the second master stage, wherein the cross-coupled circuit comprises a transistor gated by the clock signal.