US 11,863,165 B2
Input buffer
Lawrence A. Singer, Bedford, MA (US)
Assigned to Analog Devices, Inc., Wilmington, MA (US)
Filed by Analog Devices, Inc., Wilmington, MA (US)
Filed on Oct. 18, 2021, as Appl. No. 17/503,883.
Application 17/503,883 is a continuation of application No. 16/939,018, filed on Jul. 26, 2020, granted, now 11,152,931.
Application 16/939,018 is a continuation of application No. 15/689,480, filed on Aug. 29, 2017, granted, now 10,727,828, issued on Jul. 28, 2020.
Claims priority of provisional application 62/393,529, filed on Sep. 12, 2016.
Prior Publication US 2022/0216861 A1, Jul. 7, 2022
Int. Cl. H03K 17/042 (2006.01); H03K 19/017 (2006.01); H03M 1/06 (2006.01); H03M 1/12 (2006.01); H03K 17/00 (2006.01); H03K 19/0185 (2006.01); H03K 17/0412 (2006.01); H03K 17/06 (2006.01); H03M 1/18 (2006.01)
CPC H03K 17/04206 (2013.01) [H03K 17/005 (2013.01); H03K 17/04123 (2013.01); H03K 17/063 (2013.01); H03K 19/017 (2013.01); H03K 19/018521 (2013.01); H03M 1/0607 (2013.01); H03M 1/1245 (2013.01); H03M 1/183 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a ground node and a supply node, wherein the supply node is at a supply voltage with respect to the ground node;
a sampling switch to receive a voltage input signal and a gate voltage;
a bootstrapped voltage generator comprising a positive feedback loop, wherein:
the positive feedback loop is activated by a clock signal to generate the gate voltage for turning on the sampling switch; and
the positive feedback loop comprises:
an output transistor to output the gate voltage of the sampling switch;
exactly one capacitor having a first plate and a second plate, wherein the exactly one capacitor is to be charged at the supply voltage in a first phase, and the second plate is coupled to a source of the output transistor; and
an input transistor to receive the voltage input signal and the gate voltage, the input transistor to couple the voltage input signal to the first plate during a second phase; and
a jump start circuit coupled to a gate of the output transistor and configured to turn on the output transistor by decreasing a gate voltage of a gate of the output transistor toward a ground node voltage for a limited period of time during a startup of the positive feedback loop, and to cease the decreasing the gate voltage before the gate voltage reaches the ground node voltage.