US 11,862,996 B2
Pulsed level shift and inverter circuits for GaN devices
Daniel M. Kinzer, El Segundo, CA (US); Santosh Sharma, Austin, TX (US); and Ju Jason Zhang, Monterey Park, CA (US)
Assigned to Navitas Semiconductor Limited, Dublin (IE)
Filed by Navitas Semiconductor Limited, Dublin (IE)
Filed on Jul. 11, 2022, as Appl. No. 17/811,797.
Application 16/699,081 is a division of application No. 16/151,695, filed on Oct. 4, 2018, granted, now 10,530,169, issued on Jan. 7, 2020.
Application 16/151,695 is a division of application No. 15/219,248, filed on Jul. 25, 2016, granted, now 10,135,275, issued on Nov. 20, 2018.
Application 17/811,797 is a continuation of application No. 16/699,081, filed on Nov. 28, 2019, granted, now 11,404,884.
Application 15/219,248 is a continuation of application No. 14/667,523, filed on Mar. 24, 2015, granted, now 9,401,612, issued on Jul. 26, 2016.
Claims priority of provisional application 62/127,725, filed on Mar. 3, 2015.
Claims priority of provisional application 62/051,160, filed on Sep. 16, 2014.
Prior Publication US 2023/0031402 A1, Feb. 2, 2023
Int. Cl. H02M 3/158 (2006.01); H02J 7/00 (2006.01); H01L 23/495 (2006.01); H01L 27/02 (2006.01); H01L 23/62 (2006.01); H02M 1/088 (2006.01); H03K 3/012 (2006.01); H01L 29/20 (2006.01); H03K 17/10 (2006.01); H03K 19/0185 (2006.01); H01L 25/07 (2006.01); H02M 3/157 (2006.01); H03K 3/356 (2006.01); H01L 27/088 (2006.01); H01L 23/528 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H02M 1/00 (2006.01); H02M 3/155 (2006.01)
CPC H02J 7/00 (2013.01) [H01L 23/49503 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 23/528 (2013.01); H01L 23/62 (2013.01); H01L 25/072 (2013.01); H01L 27/0248 (2013.01); H01L 27/088 (2013.01); H01L 27/0883 (2013.01); H01L 29/1033 (2013.01); H01L 29/2003 (2013.01); H01L 29/402 (2013.01); H01L 29/41758 (2013.01); H02M 1/088 (2013.01); H02M 3/157 (2013.01); H02M 3/1584 (2013.01); H02M 3/1588 (2013.01); H03K 3/012 (2013.01); H03K 3/356017 (2013.01); H03K 17/102 (2013.01); H03K 19/018507 (2013.01); H01L 2924/00 (2013.01); H01L 2924/0002 (2013.01); H02M 1/0048 (2021.05); H02M 3/155 (2013.01); Y02B 40/00 (2013.01); Y02B 70/10 (2013.01)] 8 Claims
OG exemplary drawing
 
6. An electronic component comprising:
a package base;
one or more semiconductor dies secured to the package base and comprising:
a first transistor having a first gate terminal, a first source terminal and a first drain terminal; and
a second transistor having a second gate terminal, a second source terminal and a second drain terminal;
wherein the first drain terminal is coupled to the second source terminal;
wherein the first transistor is a gallium nitride (GaN)-based lateral high electron mobility transistor (HEMT) and the second transistor is a GaN-based lateral HEMT;
wherein the one or more semiconductor dies comprise a first and second GaN-based dies and a third silicon-based die, and wherein the first transistor is disposed on the first GaN-based die, the second transistor is disposed on the second GaN-based die, and wherein the third silicon-based die comprises a first gate driver circuit coupled to the first gate terminal.