US 11,862,730 B2
Top-gate doped thin film transistor
Abhishek A. Sharma, Portland, OR (US); Sean T. Ma, Portland, OR (US); Van H. Le, Beaverton, OR (US); Jack T. Kavalieros, Portland, OR (US); and Gilbert Dewey, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 27, 2022, as Appl. No. 17/826,550.
Application 17/826,550 is a continuation of application No. 15/942,169, filed on Mar. 30, 2018, granted, now 11,362,215.
Prior Publication US 2022/0328697 A1, Oct. 13, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01)
CPC H01L 29/78675 (2013.01) [H01L 29/0649 (2013.01); H01L 29/42364 (2013.01); H01L 29/42384 (2013.01); H01L 29/4908 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66757 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78666 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A top-gate thin film transistor (TFT) comprising:
a semiconductor layer doped with one or more dopant elements;
a dielectric layer adjacent to the semiconductor layer;
a gate comprising a metal, wherein the gate is adjacent to the dielectric layer;
a spacer adjacent to the gate and the dielectric layer; and
a contact adjacent to the spacer,
wherein the semiconductor layer is doped with the one or more dopant elements beneath each of the dielectric layer, the spacer, and the contact.