US 11,862,729 B2
Vertical multi-gate thin film transistors
Yih Wang, Portland, OR (US); Abhishek Sharma, Hillsboro, OR (US); Sean Ma, Portland, OR (US); and Van H. Le, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 25, 2022, as Appl. No. 17/584,260.
Application 17/584,260 is a continuation of application No. 16/490,503, granted, now 11,245,038, previously published as PCT/US2017/024969, filed on Mar. 30, 2017.
Prior Publication US 2022/0149208 A1, May 12, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 29/66 (2006.01); H10B 12/00 (2023.01)
CPC H01L 29/78642 (2013.01) [H01L 29/66742 (2013.01); H10B 12/053 (2023.02); H10B 12/34 (2023.02); H10B 12/488 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A thin film transistor structure, comprising:
a gate electrode;
a gate insulator, wherein a first sidewall of the gate insulator is adjacent to a sidewall of the gate electrode;
a channel material, wherein a sidewall of the channel material is adjacent to a second sidewall of the gate insulator;
a source contact adjacent to, and coupled with, a first sidewall portion of the channel material; and
a drain contact adjacent to, and coupled with, a second sidewall portion of the channel material.