US 11,862,728 B2
Dual gate control for trench shaped thin film transistors
Abhishek A. Sharma, Hillsboro, OR (US); Van H. Le, Beaverton, OR (US); Gilbert Dewey, Hillsboro, OR (US); Jack T. Kavalieros, Portland, OR (US); Shriram Shivaraman, Hillsboro, OR (US); Benjamin Chu-Kung, Portland, OR (US); Yih Wang, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 1, 2021, as Appl. No. 17/492,487.
Application 17/492,487 is a continuation of application No. 15/938,153, filed on Mar. 28, 2018, granted, now 11,183,594.
Prior Publication US 2022/0028861 A1, Jan. 27, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 29/08 (2006.01); H01L 29/04 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01); H10B 12/00 (2023.01); H01L 21/311 (2006.01)
CPC H01L 29/78642 (2013.01) [H01L 21/02647 (2013.01); H01L 29/04 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/42384 (2013.01); H01L 29/6656 (2013.01); H01L 29/6675 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); H10B 12/05 (2023.02); H10B 12/315 (2023.02); H10B 12/50 (2023.02); H01L 21/31116 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A thin film transistor structure, comprising:
a semiconductor layer defining a trench within first and second portions of the semiconductor layer, the first portion over a first gate dielectric layer and the second portion over a sidewall of a patterned layer, wherein the patterned layer is adjacent the first gate dielectric layer;
a first gate electrode opposite the first gate dielectric layer from the first portion of the semiconductor layer;
a second gate electrode at least partially within the trench defined by the semiconductor layer;
a second gate dielectric layer between the second gate electrode and the first portion of the semiconductor layer; and
a source and a drain coupled to the semiconductor layer.