CPC H01L 29/78391 (2014.09) [H01L 29/6684 (2013.01); H10B 51/00 (2023.02)] | 20 Claims |
1. A transistor, comprising:
an insulating layer;
a source region and a drain region respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer, wherein a top surface of the source region, a top surface of the drain region, and a top surface of the insulating layer are substantially coplanar;
a channel layer disposed on the insulating layer, the source region, and the drain region;
a ferroelectric layer disposed over the channel layer;
an interfacial layer sandwiched between the channel layer and the ferroelectric layer; and
a gate electrode disposed on the ferroelectric layer.
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