US 11,862,726 B2
Transistor, integrated circuit, and manufacturing method of transistor
Hung-Chang Sun, Kaohsiung (TW); Sheng-Chih Lai, Hsinchu County (TW); Yu-Wei Jiang, Hsinchu (TW); Kuo-Chang Chiang, Hsinchu (TW); Tsuching Yang, Taipei (TW); Feng-Cheng Yang, Hsinchu County (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 13, 2021, as Appl. No. 17/401,315.
Prior Publication US 2023/0049651 A1, Feb. 16, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 29/66 (2006.01); H10B 51/00 (2023.01)
CPC H01L 29/78391 (2014.09) [H01L 29/6684 (2013.01); H10B 51/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A transistor, comprising:
an insulating layer;
a source region and a drain region respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer, wherein a top surface of the source region, a top surface of the drain region, and a top surface of the insulating layer are substantially coplanar;
a channel layer disposed on the insulating layer, the source region, and the drain region;
a ferroelectric layer disposed over the channel layer;
an interfacial layer sandwiched between the channel layer and the ferroelectric layer; and
a gate electrode disposed on the ferroelectric layer.