US 11,862,725 B2
Transistors with schottky barriers
Yun Shi, San Diego, CA (US); and John Tzung-Yin Lee, Costa Mesa, CA (US)
Assigned to Skyworks Solutions, Inc., Irvine, CA (US)
Filed by SKYWORKS SOLUTIONS, INC., Irvine, CA (US)
Filed on Aug. 15, 2022, as Appl. No. 17/888,351.
Application 17/888,351 is a continuation of application No. 16/911,677, filed on Jun. 25, 2020, granted, now 11,417,762.
Claims priority of provisional application 62/866,737, filed on Jun. 26, 2019.
Prior Publication US 2023/0038868 A1, Feb. 9, 2023
Int. Cl. H01L 21/02 (2006.01); H01L 27/02 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H03K 17/687 (2006.01); H03F 3/24 (2006.01)
CPC H01L 29/7839 (2013.01) [H03K 17/6871 (2013.01); H03F 3/245 (2013.01); H03F 2200/451 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a transistor, the method comprising:
forming a p-well or an n-well in a substrate;
forming a gate for the transistor;
doping a first region within the p-well or the n-well with a concentration that is below a threshold to form a source for the transistor;
doping a second region within the p-well or the n-well with the concentration to form a drain for the transistor, at least a portion of the p-well or the n-well being disposed between the source and the drain of the transistor; and
forming a first contact on the first region and a second contact on the second region.