US 11,862,707 B2
HEMT transistor of the normally off type including a trench containing a gate region and forming at least one step, and corresponding manufacturing method
Ferdinando Iucolano, Gravina di Catania (IT); Alfonso Patti, Tremestieri Etneo (IT); and Alessandro Chini, Modena (IT)
Assigned to STMICROELECTRONICS S.R.L., Agrate Brianza (IT)
Filed by STMICROELECTRONICS S.R.L., Agrate Brianza (IT)
Filed on Aug. 6, 2021, as Appl. No. 17/396,154.
Application 16/690,035 is a division of application No. 15/159,045, filed on May 19, 2016, granted, now 10,522,646, issued on Dec. 31, 2019.
Application 17/396,154 is a continuation of application No. 16/690,035, filed on Nov. 20, 2019, granted, now 11,101,363.
Claims priority of application No. 102015000072111 (IT), filed on Nov. 12, 2015.
Prior Publication US 2021/0367062 A1, Nov. 25, 2021
Int. Cl. H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/778 (2006.01); H01L 29/205 (2006.01); H01L 29/20 (2006.01)
CPC H01L 29/66462 (2013.01) [H01L 29/205 (2013.01); H01L 29/4236 (2013.01); H01L 29/42376 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01); H01L 29/2003 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A normally off heterostructure field-effect transistor (HEMT), comprising:
a semiconductor heterostructure including:
a first semiconductor layer formed by gallium nitride; and
a second semiconductor layer formed by aluminum gallium nitride;
a passivation layer of dielectric material on the semiconductor heterostructure;
a trench in the passivation layer and the semiconductor heterostructure, the trench including:
a bottom surface;
a planar vertical sidewall in the semiconductor heterostructure on a first side of the trench; and
a plurality of first steps each including a respective horizontal surface higher in the trench than the bottom surface and a respective vertical surface laterally opposite the planar vertical sidewall on a second side of the trench in the semiconductor heterostructure, wherein the planar vertical sidewall extends entirely through the second semiconductor layer.