US 11,862,690 B2
Method of manufacturing a semiconductor device
Ming-Wen Hsiao, Kaohsiung (TW); Chun-Yen Tai, Hsinchu (TW); Yen-Hsin Liu, New Taipei (TW); Ming-Jhih Kuo, Zhubei (TW); and Ming-Feng Shieh, Yongkang (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Apr. 23, 2021, as Appl. No. 17/239,254.
Prior Publication US 2022/0344478 A1, Oct. 27, 2022
Int. Cl. H01L 29/40 (2006.01); H01L 21/027 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01)
CPC H01L 29/401 (2013.01) [H01L 21/0273 (2013.01); H01L 21/76895 (2013.01); H01L 29/41775 (2013.01); H01L 29/41791 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming underlying structures comprising gate electrodes and source/drain epitaxial layers over a substrate;
forming one or more layers over the underlying structures;
forming a hard mask layer over the one or more layers;
forming one or more first resist layers over the hard mask layer;
forming a first photo resist pattern over the one or more first resist layers;
adjusting a width of the first photo resist pattern;
patterning the one or more first resist layers by using the first photo resist pattern as an etching mask, thereby forming a first mask pattern;
patterning the hard mask layer by using the first mask pattern, thereby forming a second hard mask pattern;
forming one or more second resist layers over the second hard mask pattern;
forming a third mask pattern by patterning the one or more second resist layers; and
patterning the one or more layers by using the third mask pattern and the second hard mask pattern as an etching mask, thereby forming a fourth mask pattern.