US 11,862,675 B2
High voltage metal-oxide-semiconductor (HVMOS) device integrated with a high voltage junction termination (HVJT) device
Karthick Murukesan, Hsinchu (TW); Wen-Chih Chiang, Hsinchu (TW); Chun Lin Tsai, Hsin-Chu (TW); Ker-Hsiao Huo, Zhubei (TW); Kuo-Ming Wu, Hsinchu (TW); Po-Chih Chen, Hsinchu (TW); Ru-Yi Su, Kouhu Township (TW); Shiuan-Jeng Lin, Hsinchu (TW); Yi-Min Chen, Hsinchu (TW); Hung-Chou Lin, Douliu (TW); and Yi-Cheng Chiu, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 31, 2021, as Appl. No. 17/462,403.
Application 17/462,403 is a continuation of application No. 16/601,998, filed on Oct. 15, 2019, granted, now 11,145,713.
Application 16/601,998 is a continuation of application No. 15/964,636, filed on Apr. 27, 2018, granted, now 10,535,730, issued on Jan. 14, 2020.
Claims priority of provisional application 62/564,695, filed on Sep. 28, 2017.
Prior Publication US 2021/0399087 A1, Dec. 23, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H03K 19/0185 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/063 (2013.01) [H01L 21/823481 (2013.01); H01L 21/823493 (2013.01); H01L 27/088 (2013.01); H01L 29/0634 (2013.01); H01L 29/1095 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01); H03K 19/018507 (2013.01); H01L 21/823418 (2013.01); H01L 21/823892 (2013.01); H01L 27/0922 (2013.01); H01L 29/0696 (2013.01); H01L 29/0847 (2013.01); H01L 29/0886 (2013.01); H01L 29/404 (2013.01); H01L 29/42368 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a substrate;
a termination device well in the substrate and having a first doping type;
a switching device bordering the termination device well on the substrate, wherein the switching device comprises a pair of source/drain regions and a gate electrode between the pair of source/drain regions;
a peripheral well in the substrate and having a second doping type opposite the first doping type, wherein the peripheral well is spaced from the pair of source/drain regions of the switching device and separates and individually surrounds the switching device and the termination device well;
a high side well overlying the termination device well in the substrate and having the second doping type, wherein the high side well has a sidewall boundary directly contacting the termination device well continuously in a first closed path;
a dielectric structure sunken into the substrate;
a spiral structure overlying the switching device and the dielectric structure; and
a contact region overlying the termination device well in the substrate and having the first doping type, wherein the contact region is spaced from the high side well and extends along the sidewall boundary continuously in a second closed path, and wherein the dielectric structure is continuous linearly from the contact region to the spiral structure.