US 11,862,662 B2
Image device
Sotetsu Saito, Kanagawa (JP); Suguru Saito, Kanagawa (JP); and Nobutoshi Fujii, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/279,352
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Oct. 9, 2019, PCT No. PCT/JP2019/039744
§ 371(c)(1), (2) Date Mar. 24, 2021,
PCT Pub. No. WO2020/090384, PCT Pub. Date May 7, 2020.
Claims priority of application No. 2018-202769 (JP), filed on Oct. 29, 2018.
Prior Publication US 2021/0408092 A1, Dec. 30, 2021
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/1469 (2013.01) [H01L 27/14634 (2013.01); H01L 27/14636 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An imaging device comprising
an imaging element, and a semiconductor element provided to be opposed to the imaging element and electrically coupled to the imaging element, wherein
the semiconductor element includes:
a wiring region provided in a middle portion and a peripheral region outside the wiring region;
a wiring layer having a wiring line in the wiring region;
a semiconductor substrate opposed to the imaging element with the wiring layer interposed therebetween and having a first surface and a second surface in order from a side of the wiring layer; and
a polishing adjustment section including a material that is lower in polishing rate than a constituent material of the semiconductor substrate, the polishing adjustment section being disposed in at least a portion of the peripheral region and provided in a thickness direction of the semiconductor substrate from the second surface.