US 11,862,657 B2
Semiconductor package and camera module
Osamu Shirata, Tokyo (JP); and Yusuke Hidaka, Tokyo (JP)
Assigned to Asahi Kasei Microdevices Corporation, Tokyo (JP)
Filed by ASAHI KASEI MICRODEVICES CORPORATION, Tokyo (JP)
Filed on Jul. 1, 2022, as Appl. No. 17/856,309.
Application 17/856,309 is a continuation of application No. 17/001,738, filed on Aug. 25, 2020, granted, now 11,411,038.
Application 17/001,738 is a continuation of application No. 16/202,665, filed on Nov. 28, 2018, granted, now 10,790,328, issued on Sep. 29, 2020.
Claims priority of application No. 2017-227584 (JP), filed on Nov. 28, 2017; and application No. 2018-200361 (JP), filed on Oct. 24, 2018.
Prior Publication US 2022/0336516 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/146 (2006.01); H04N 23/54 (2023.01)
CPC H01L 27/14636 (2013.01) [H01L 27/14618 (2013.01); H01L 27/14627 (2013.01); H04N 23/54 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising terminals,
wherein the semiconductor package has a width and a length as viewed in plan, the length being greater than the width,
wherein, for any three terminals from among all of the terminals, an angle formed by two line segments connecting a center of gravity of a terminal positioned in a center in a longitudinal direction and a center of gravity of each of the other two terminals is 60° or more,
wherein the width L1 of the semiconductor package and a distance Lt between a rightmost end position of a terminal arranged at a rightmost end in a width direction of the semiconductor package among all of the terminals and a leftmost end position of a terminal arranged at a leftmost end in the width direction satisfy Lt/L1≥0.5,
wherein all of the terminals are spaced apart from a line segment passing through a center in the width direction of the semiconductor package with a first center of gravity of a first portion of all the terminals arranged on a first side across the line segment and a second center of gravity of a second portion of all the terminals other than the first portion arranged on a second side across the line segment,
wherein a number of terminals in the first portion and a number terminals in the second portion are equal, and
wherein the semiconductor package is a wafer level chip size.