CPC H01L 27/0924 (2013.01) [H01L 21/02532 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/16 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/785 (2013.01)] | 19 Claims |
1. A semiconductor device, comprising:
a first semiconductor layer including a first region and a second region;
a plurality of first channel layers spaced apart from each other in a vertical direction on the first semiconductor layer in the first region;
a first gate electrode surrounding the plurality of first channel layers;
a plurality of second channel layers spaced apart from one another in the vertical direction on the first semiconductor layer in the second region; and
a second gate electrode surrounding the plurality of second channel layers,
wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation,
wherein the plurality of first channel layers include a first lowermost channel layer closest to the first semiconductor layer among the plurality of first channel layers,
wherein the plurality of second channel layers include a second lowermost channel layer closest to the first semiconductor layer among the plurality of second channel layers, and
wherein a level of a lower surface of the first lowermost channel layer is different from a level of a lower surface of the second lowermost channel layer.
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