US 11,862,638 B2
Semiconductor device and method
Shahaji B. More, Hsinchu (TW); and Chandrashekhar Prakash Savant, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 24, 2021, as Appl. No. 17/211,109.
Claims priority of provisional application 63/082,530, filed on Sep. 24, 2020.
Claims priority of provisional application 63/065,557, filed on Aug. 14, 2020.
Prior Publication US 2022/0052045 A1, Feb. 17, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 29/6656 (2013.01); H01L 29/6681 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a dummy gate over a channel region of a fin;
forming gate spacers adjacent the dummy gate;
recessing the dummy gate to expose sidewalls of the gate spacers;
performing a spacer treatment process, the spacer treatment process bowing the sidewalls of the gate spacers inwardly towards one another in a top-down view such that a distance between the sidewalls of the gate spacers is decreased by the spacer treatment process;
removing remaining portions of the dummy gate to expose the channel region; and
forming a gate dielectric on the channel region and the sidewalls of the gate spacers.