US 11,862,637 B2
Tie off device
Shao-Lun Chien, Hsinchu (TW); Ting-Wei Chiang, New Taipei (TW); Hui-Zhong Zhuang, Kaohsiung (TW); and Pin-Dai Sue, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 20, 2020, as Appl. No. 16/879,166.
Claims priority of provisional application 62/863,387, filed on Jun. 19, 2019.
Prior Publication US 2020/0402979 A1, Dec. 24, 2020
Int. Cl. H01L 27/092 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 21/765 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/765 (2013.01); H01L 21/823412 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 27/0922 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a first power rail;
a first active area extending in a first direction, the first active area including a first region defining a first threshold voltage (VT) and a second region defining a second VT different than the first VT, the first and second regions abutting one another to define a boundary therebetween;
a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction;
a first transistor including the first region of the first active area and a first one of the gates, the first transistor having the first VT;
a second transistor including the second region of the first active area and a second one of the gates, the second transistor having the second VT; and
a tie-off transistor positioned at the boundary of the first region and the second region such that the first transistor is on a first side of the boundary in the first direction and the second transistor is on a second side of the boundary in the first direction, the tie-off transistor including the first active area and a third one of the gates, wherein the third gate is positioned directly over the boundary and is connected to the first power rail.