US 11,862,628 B2
Transistor configurations for multi-deck memory devices
Fatma Arzum Simsek-Ege, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 20, 2021, as Appl. No. 17/326,286.
Prior Publication US 2022/0375930 A1, Nov. 24, 2022
Int. Cl. H01L 27/06 (2006.01); G11C 5/06 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 27/0688 (2013.01) [G11C 5/06 (2013.01); H01L 21/8238 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 25/0657 (2013.01); H01L 27/092 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
forming, based at least in part on doping portions of a first silicon substrate, a first plurality of transistors;
forming a first deck of memory cells above the first silicon substrate and coupled with the first plurality of transistors;
forming a second deck of memory cells above the first deck of memory cells;
bonding a second silicon substrate above the second deck of memory cells;
forming, based at least in part on doping portions of the second silicon substrate after bonding the second silicon substrate above the second deck of memory cells, a second plurality of transistors coupled with the second deck of memory cells; and
forming, after bonding the second silicon substrate above the second deck of memory cells, a first plurality of interconnects, wherein each interconnect couples one or more subsets of transistors of the first plurality of transistors with one or more subsets of transistors of the second plurality of transistors.