US 11,862,625 B2
Area-efficient ESD protection inside standard cells
Michael A. Stockinger, Austin, TX (US); Mohamed Suleman Moosa, Austin, TX (US); Vasily Vladimirovich Korolev, Moscow (RU); Irina Yuryevna Bashkirova, Moscow (RU); and Olga Olegovna Sibagatullina, Moscow (RU)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Jan. 10, 2022, as Appl. No. 17/647,531.
Claims priority of application No. RU202119348 (RU), filed on Jul. 1, 2021.
Prior Publication US 2023/0223394 A1, Jul. 13, 2023
Int. Cl. H01L 27/02 (2006.01); H02H 9/04 (2006.01)
CPC H01L 27/0255 (2013.01) [H01L 27/0266 (2013.01); H02H 9/046 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a signal node coupled to receive an electrostatic discharge voltage from a transmitting circuit;
an electrostatic discharge protection circuit connected between a first voltage supply and a second voltage supply, comprising:
a first FinFET diode connected between the signal node and the first voltage supply, and
a second FinFET diode connected between the signal node and the second voltage supply; and
a protected circuit comprising a first FinFET operably coupled to the signal node that is protected against electrostatic discharge voltage damage by the electrostatic discharge protection circuit,
where the first and second FinFET diodes are each formed with a finFET device comprising (1) a body well region forming a first diode terminal connected to one of the first or second voltage supplies, and (2) shorted gate, source, and drain regions forming a second diode terminal connected to the signal node.