US 11,862,600 B2
Method of forming a chip package and chip package
Thorsten Scharf, Lappersdorf (DE); Alexander Heinrich, Bad Abbach (DE); and Steffen Jordan, Pielenhofen (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Oct. 1, 2021, as Appl. No. 17/491,647.
Claims priority of application No. 102020125813.5 (DE), filed on Oct. 2, 2020.
Prior Publication US 2022/0108974 A1, Apr. 7, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01)
CPC H01L 24/80 (2013.01) [H01L 21/565 (2013.01); H01L 23/4985 (2013.01); H01L 2224/80357 (2013.01); H01L 2224/83385 (2013.01); H01L 2924/1511 (2013.01); H01L 2924/15724 (2013.01); H01L 2924/15738 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method of forming a chip package, the method comprising:
providing a malleable carrier with a layer of an electrically conductive material formed thereon; and
positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier such that the malleable carrier conforms to outer edge sides of the chip,
wherein the layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip,
wherein the layer forms a redistribution layer.