US 11,862,595 B2
Packaging method for fan-out wafer-level packaging structure
Hailin Zhao, Jiangyin (CN)
Assigned to SJ SEMICONDUCTOR(JIANGYIN) CORPORATION, Jiangyin (CN)
Filed by SJ Semiconductor(Jiangyin) Corporation, Jiangyin (CN)
Filed on Sep. 8, 2021, as Appl. No. 17/469,783.
Claims priority of application No. 202010935518.X (CN), filed on Sep. 8, 2020.
Prior Publication US 2022/0077096 A1, Mar. 10, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 21/683 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/19 (2013.01) [H01L 24/11 (2013.01); H01L 24/73 (2013.01); H01L 25/50 (2013.01); H01L 21/6836 (2013.01); H01L 25/0655 (2013.01); H01L 2224/73209 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/07025 (2013.01); H01L 2924/186 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/37001 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A packaging method for a fan-out wafer-level packaging structure, wherein the packaging method comprises:
providing two or more semiconductor chips, each of which has one or more pads, and bonding the semiconductor chips to a bonding layer to form a fan-out wafer array;
packaging the semiconductor chips by a plastic packaging layer;
removing the bonding layer, and forming a redistribution layer on the semiconductor chips to achieve interconnection between the semiconductor chips, wherein the redistribution layer comprises one or more redistribution sublayers stacked in sequence, wherein a first redistribution sublayer is in contact of the one or more pads;
wherein a method for forming each of the one or more redistribution sublayers comprises:
forming a dielectric layer on the semiconductor chips, wherein a warpage is generated in a forming process of the dielectric layer;
forming vias in the dielectric layer by photolithography;
baking the dielectric layer having the vias formed therein, wherein baking the dielectric layer eliminates the warpage on the dielectric layer around the vias;
curing the fan-out wafer array; and
forming a patterned metal distribution layer in the vias and on the dielectric layer, with the pattern of the patterned metal distribution layer corresponding to the layout of the vias;
and
forming metal bumps on the redistribution layer.