US 11,862,579 B2
Semiconductor device having cavities at an interface of an encapsulant and a die pad or leads
Ian Harvey Arellano, Bauang (PH)
Assigned to STMicroelectronics, Inc., Coppell, TX (US)
Filed by STMICROELECTRONICS, INC., Calamba (PH)
Filed on Jun. 21, 2022, as Appl. No. 17/845,867.
Application 17/845,867 is a division of application No. 16/996,712, filed on Aug. 18, 2020, granted, now 11,393,774.
Claims priority of provisional application 62/889,841, filed on Aug. 21, 2019.
Prior Publication US 2022/0320014 A1, Oct. 6, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/4825 (2013.01); H01L 21/565 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49513 (2013.01); H01L 23/49548 (2013.01); H01L 23/49582 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a semiconductor device by:
forming a conductive layer on a conductive substrate, the conductive layer including a plurality of microstructures at least partially embedded in the conductive layer;
forming a plurality of cavities in the conductive layer by removing the plurality of microstructures; and
at least partially filling the plurality of cavities with an encapsulation material.