US 11,862,553 B2
Semiconductor device
Hidetaka Matsuo, Tokyo (JP); Ryo Goto, Tokyo (JP); and Yasutaka Shimizu, Tokyo (JP)
Assigned to Mitsubishi Electric Corporation, Tokyo (JP)
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
Filed on Nov. 15, 2021, as Appl. No. 17/454,888.
Claims priority of application No. 2021-023139 (JP), filed on Feb. 17, 2021.
Prior Publication US 2022/0262717 A1, Aug. 18, 2022
Int. Cl. H01L 23/50 (2006.01); H01L 25/07 (2006.01)
CPC H01L 23/50 (2013.01) [H01L 25/072 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an insulating substrate;
a circuit pattern including a circuit pattern on a low potential side provided on the insulating substrate and a circuit pattern on a high potential side provided in a region adjacent to the circuit pattern on the low potential side on the insulating substrate;
a plurality of semiconductor chips mounted on the circuit pattern;
a low potential terminal having one end portion connected to the circuit pattern on the low potential side; and
a high potential terminal having one end portion connected to the circuit pattern on the high potential side, wherein
the insulating substrate is a single insulating substrate, and
the high potential terminal and the low potential terminal include a midway portion constituting parallel flat plates vertical disposed in parallel to each other and extending on a side of the circuit pattern on the low potential side and another end portion protruding from the insulating substrate.