US 11,862,535 B2
Through-substrate-via with reentrant profile
Hung-Ling Shih, Tainan (TW); Wei Chuang Wu, Tainan (TW); Shih Kuang Yang, Tainan (TW); Hsing-Chih Lin, Tainan (TW); and Jen-Cheng Liu, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 17, 2021, as Appl. No. 17/177,660.
Claims priority of provisional application 63/079,003, filed on Sep. 16, 2020.
Prior Publication US 2022/0084908 A1, Mar. 17, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 21/308 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/308 (2013.01); H01L 21/76804 (2013.01); H01L 21/76831 (2013.01); H01L 21/76898 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a semiconductor device arranged along a first side of a semiconductor substrate, wherein the semiconductor substrate comprises one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate;
a dielectric liner lining the one or more sidewalls of the semiconductor substrate;
a through-substrate-via (TSV) arranged between the one or more sidewalls and separated from the semiconductor substrate by the dielectric liner; and
wherein the dielectric liner has sidewalls that slope inward towards one another from an upper surface of the dielectric liner arranged directly below the TSV to a topmost surface of the dielectric liner over the one or more sidewalls of the semiconductor substrate, so that the dielectric liner overhangs the TSV in a cross-sectional view.