US 11,862,514 B2
Integrated circuit device including air gaps and method of manufacturing the same
Sanghoon Ahn, Seongnam-si (KR); Woojin Lee, Suwon-si (KR); and Kyuhee Han, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 10, 2022, as Appl. No. 17/984,874.
Application 17/984,874 is a continuation of application No. 16/872,955, filed on May 12, 2020, granted, now 11,515,201.
Claims priority of application No. 10-2019-0134103 (KR), filed on Oct. 25, 2019.
Prior Publication US 2023/0072375 A1, Mar. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H10B 12/00 (2023.01); H01L 23/48 (2006.01); H01L 23/28 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76834 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 21/76895 (2013.01); H01L 23/28 (2013.01); H01L 23/48 (2013.01); H10B 12/482 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing an integrated circuit device, the method comprising:
forming a lower wiring structure and a first sacrificial pattern on the lower wiring structure;
conformally forming an insulating barrier layer on the lower wiring structure and the first sacrificial pattern;
forming a second sacrificial pattern to fill a portion of an opening defined by the insulating barrier layer;
forming a capping layer on the second sacrificial pattern and the insulating barrier layer;
polishing the capping layer and the insulating barrier layer until an upper surface of the first sacrificial pattern is exposed;
removing the first sacrificial pattern;
forming an air gap by removing the second sacrificial pattern;
conformally forming an etch stop layer on the lower wiring structure, the insulating barrier layer, and the capping layer;
forming an insulating layer on the etch stop layer; and
forming an upper wiring structure penetrating the insulating layer.