US 11,862,435 B2
Mechanical suppression of parasitic plasma in substrate processing chamber
Douglas Keil, West Linn, OR (US); Edward J. Augustyniak, Tualatin, OR (US); Karl Frederick Leeser, West Linn, OR (US); and Mohamed Sabri, Beaverton, OR (US)
Assigned to Lam Research Corporation, Fremont, CA (US)
Filed by Lam Research Corporation, Fremont, CA (US)
Filed on Mar. 31, 2023, as Appl. No. 18/129,370.
Application 16/267,932 is a division of application No. 13/303,386, filed on Nov. 23, 2011, granted, now 10,224,182.
Application 18/129,370 is a continuation of application No. 16/267,932, filed on Feb. 5, 2019, granted, now 11,621,150.
Claims priority of provisional application 61/547,962, filed on Oct. 17, 2011.
Prior Publication US 2023/0238220 A1, Jul. 27, 2023
Int. Cl. H01J 37/32 (2006.01); C23C 16/455 (2006.01)
CPC H01J 37/32495 (2013.01) [C23C 16/45565 (2013.01); H01J 37/3244 (2013.01); H01J 37/32623 (2013.01); H01J 37/3255 (2013.01); H01J 37/32091 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method for creating a high impedance path for reducing parasitic plasma in a process chamber including an electrode and a conducting structure, the method comprising:
selecting a number of a plurality of dielectric layers to arrange between the electrode and a first surface of the conducting structure;
selecting respective sizes of (i) a first gap between the electrode and a first one of the plurality of dielectric layers, (ii) a second gap between adjacent ones of the plurality of dielectric layers, and (iii) a third gap between a last one of the plurality of dielectric layers and the first surface,
wherein selecting the number of the plurality of dielectric layers and the respective sizes includes selecting the number of the plurality of dielectric layers and the respective sizes to prevent parasitic plasma between the first surface and the electrode during a semiconductor process performed in the process chamber; and
vertically arranging the selected number of the plurality of dielectric layers in a vertical stack between the electrode and the first surface of the conducting structure in accordance with the selected respective sizes of the first gap, the second gap, and the third gap.