US 11,862,274 B2
Determination of state metrics of memory sub-systems following power events
Michael Sheperek, Longmont, CO (US); Bruce A. Liikanen, Berthoud, CO (US); and Steven Michael Kientz, Westminster, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 1, 2023, as Appl. No. 18/116,028.
Application 18/116,028 is a division of application No. 17/301,348, filed on Mar. 31, 2021, granted, now 11,600,354.
Claims priority of provisional application 62/706,455, filed on Aug. 18, 2020.
Prior Publication US 2023/0207043 A1, Jun. 29, 2023
Int. Cl. G11C 29/44 (2006.01); G11C 29/12 (2006.01); G11C 29/42 (2006.01)
CPC G11C 29/44 (2013.01) [G11C 29/12005 (2013.01); G11C 29/12015 (2013.01); G11C 29/42 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device to perform operations comprising:
associating a first block family with a first bin of a plurality of bins, each of the plurality of bins associated with one or more read voltage offsets, wherein the read voltage offsets are to compensate for a temporal read voltage shift caused by a charge loss by memory cells of the first block family; and
responsive to an occurrence of a power event, performing diagnostics of one or more blocks of the first block family; and
based on results of the diagnostics, associating the first block family with a second bin of the plurality of bins.