US 11,862,268 B2
Test method for control chip and related device
Chuanqi Shi, Hefei (CN); Heng-Chia Chang, Hefei (CN); Li Ding, Hefei (CN); Jie Liu, Hefei (CN); Jun He, Hefei (CN); and Zhan Ying, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/595,456
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Oct. 15, 2020, PCT No. PCT/CN2020/121299
§ 371(c)(1), (2) Date Nov. 17, 2021,
PCT Pub. No. WO2021/179603, PCT Pub. Date Sep. 16, 2021.
Claims priority of application No. 202010167247.8 (CN), filed on Mar. 11, 2020.
Prior Publication US 2022/0223219 A1, Jul. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/10 (2006.01); G11C 29/36 (2006.01); G11C 29/56 (2006.01); G11C 29/40 (2006.01)
CPC G11C 29/10 (2013.01) [G11C 29/36 (2013.01); G11C 29/56 (2013.01); G11C 29/56004 (2013.01); G11C 2029/4002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A test method for a control chip, comprising:
reading, by automatic test equipment (ATE), first test vectors stored in a first target memory chip;
sending, by the ATE, the first test vectors to the control chip;
receiving, by the ATE, first output information returned by the control chip in response to the first test vectors; and
acquiring, by the ATE, a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information.