US 11,862,258 B2
Memory device and operating method thereof
Hyun Seob Shin, Gyeonggi-do (KR); Dong Hun Kwak, Gyeonggi-do (KR); and Sung Hyun Hwang, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Nov. 19, 2021, as Appl. No. 17/531,458.
Claims priority of application No. 10-2021-0083213 (KR), filed on Jun. 25, 2021.
Prior Publication US 2022/0415419 A1, Dec. 29, 2022
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/16 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3495 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An operating method of a memory device, comprising:
a program operation of applying a program voltage to a selected word line to program selected memory cells connected to the selected word line;
a first verification operation of applying a first verification voltage to the selected word line and applying a first verification pass voltage to unselected word lines to verify a first program state of the selected memory cells; and
a second verification operation of applying a second verification voltage, which has a higher level than the first verification voltage, to the selected word line and applying a second verification pass voltage, which has a higher level than the first verification pass voltage, to the unselected word lines to verify a second program state higher than the first program state of the selected memory cells.