CPC G11C 16/26 (2013.01) [G11C 16/08 (2013.01); G11C 16/32 (2013.01); G11C 16/10 (2013.01); H03K 19/20 (2013.01)] | 15 Claims |
1. A data output control circuit comprising:
a dividing circuit configured to divide read enable signals to generate multiple phase clock signals;
a timing signal generating circuit configured to generate a plurality of timing signals based on warming-up cycle information and the multiple phase clock signals; and
a control signal generating circuit configured to generate data output control signals based on the multiple phase clock signals and the plurality of timing signals.
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