US 11,862,253 B2
Data output control circuit and semiconductor apparatus including the same
Kwang Soon Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 18, 2022, as Appl. No. 17/578,156.
Claims priority of application No. 10-2021-0114791 (KR), filed on Aug. 30, 2021.
Prior Publication US 2023/0064351 A1, Mar. 2, 2023
Int. Cl. G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/08 (2006.01); H03K 19/20 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/08 (2013.01); G11C 16/32 (2013.01); G11C 16/10 (2013.01); H03K 19/20 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A data output control circuit comprising:
a dividing circuit configured to divide read enable signals to generate multiple phase clock signals;
a timing signal generating circuit configured to generate a plurality of timing signals based on warming-up cycle information and the multiple phase clock signals; and
a control signal generating circuit configured to generate data output control signals based on the multiple phase clock signals and the plurality of timing signals.